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Root cause analysis at Savannah River plant nuclear power station - Root, cause, analysis, at, Savannah, River, plant, [nuclear, power, station], Abstract , A, method, has, been, developed, at, Savannah, River, plant, (USA), to, systematically, evaluate, events, identify, their, root, causes, record, the, root, causes, and, analyze, the, root, trends., By, providing, a, systematic, method, to, identify, correctable, root, causes, the, system, helps, the, event, investigator, ask, the, right, questions, during, the, investigation., It, also, provides, an, independent, safety, analysis, group, and, management, with, statistics, indicating, existing, and, developing, trouble, spots., An, example, demonstrating, the, usefulness, of, the, root, analysis, tree, is, presented - sciencestage.com Engineering
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Using Magnetic Regulators for the Optimization of Universal Ballasts - Using, Magnetic, Regulators, for, the, Optimization, of, Universal, Ballasts, Abstract , Nowadays, there, are, few, commercial, types, of, ballasts, that, are, able, to, control, fluorescent, lamps, with, different, power, ratings., One, of, the, main, issues, is, how, to, get, optimum, operation, for, each, lamp, in, this, condition., This, paper, tries, to, demonstrate, how, to, accomplish, this, objective, using, a, magnetic, regulator, i.e., using, a, variable, inductor., This, variable, inductor, is, controlled, by, a, dc, current, delivered, by, a, forward, converter, directly, supplied, from, the, ballast, dc, bus, voltage., This, control, current, allows, changing, the, resonant, tank, and, adapting, it, to, the, working, parameters, imposed, by, each, lamp, ensuring, near-resonance, working, conditions., Design, criteria, and, practical, verifications, are, included, to, confirm, this, new, technique., Theoretical, predictions, are, verified, with, the, experimental, results, for, three, TLD, Philips, fluorescent, lamps, from, 18, to, 58, W. - sciencestage.com Engineering
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Algorithm for VLSI chip floor plan - Algorithm, for, VLSI, chip, floor, plan, Abstract , An, algorithm, for, a, VLSI, chip, floor, plan, is, presented., It, uses, initial, block, placement, obtained, by, the, AR, (attractive, and, repulsive, force), method, and, performs, iterative, block, packing, by, gradually, moving, and, reshaping, blocks, with, chip, boundary, shrinking., By, the, use, of, several, types, of, experimental, data, it, is, shown, that, the, method, is, very, effective, for, handling, various, types, of, blocks, and, is, well, suited, to, interactive, chip, layout, design. - sciencestage.com Engineering
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